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Feature Article

Feature Article

Modeling Vertical Tunnel FET

The Tunnel FET or TFET has been identified as a possible future elementary transistor for future fast low-power applications, surpassing CMOS performance. Min and Asbeck of the University of California at San Diego have simulated such a device in a novel vertical configuration, and report the results in the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC): “Compact Modeling of Distributed Effects in 2-D Vertical Tunnel FETs and Their Impact on DC and RF Performances.” Their results indicate an 800 GHz cutoff frequency for a 20 nm channel length, even including parasitics. This is highly encouraging for high-frequency analog and digital applications.

Technology Spotlight

Technology Spotlight

HPE Video: Moore’s Law is Dead - What Comes Next?

HPE sponsored Discover 2017 in Las Vegas, Nevada, June 5-8, 2017, exploring some novel technologies for the future of computing. This video includes presentations by Kirk Bresniker, John Paul Strachan, and Thomas Vaerenbergh on memory-driven digital computing, memristor-based analog computing, and silicon photonic computing.

Watch the video here.

Other videos from the same conference are available here.