- Stochastic Computing in a Single Device - Minnesota researchers demonstrate magnetic tunnel junction which processes logic using random bits.
- Continuing progress internationally in moving toward exascale computers - Approaches to reduce power requirements include improved memory architectures and GPUs.
- Microsoft Announces Quantum Development Kit - Microsoft has publicly released a Quantum Development Kit, a software environment for developing applications of quantum computing.
- Green500 Drives Power Efficiency for Exascale - List of most power efficient supercomputers shows continued improvement in Gigaflops/Watt.
- In-Memory Computing Demonstrated using Phase-Change Memories - IBM researchers demonstrated accelerated machine learning in PCM memory array.
- Next-Generation Resistive RAM being developed - ReRAMs are fast non-volatile switches for memories and neural networks.
- Stanford Researchers Demonstrate New Ultrathin Semiconductors - HfSe2 and ZrSe2 semiconductors function in layers as thin as 3 atoms, and form passivating oxides.
- US Timeline for Exascale Computing - US Dept. of Energy labs plan demonstration of exascale system by 2023.
- Testing Brain-Inspired Chips for Big Data Problems at Berkeley Lab - IBM True North Chips applied to complex image analysis in high-energy physics, structural biology, materials science, and cosmology.
Beyond CMOS Computing:
The Interconnect Challenge Workshop held in Annapolis, Maryland, Nov. 29, 2017.
This workshop addressed the fact that data transfer between logic and memory has increasingly become the major bottleneck in computer speed and energy. Ways to deal with this problem include alternative architectures and computing paradigms (neuromorphic, approximate, 3D, analog, quantum) and alternative interconnect technologies (optical, superconducting, graphene). The agenda is available here, and the slide presentations for many of the talks are available.
The keynote address was given by Irene Qualters, the Director of the Division of Advanced Cyber-infrastructure at the US National Science Foundation. Her presentation is available here (PDF, 3 MB). She emphasizes that the interconnect challenge is at the heart of modern computing, with no single solution likely. A variety of complementary approaches in research and development are needed throughout the computing stack, requiring contributions and coordination among government, industry, and academia.
Industry Summit on the Future of Computing 2017, November, Washington DC:
“Removing the Handcuffs: Computing at the End of Moore’s Scaling,” by Dr. R. Stanley Williams of HPE.
The IEEE Industry Summit on the Future of Computing was held on Nov. 10, 2017 as part of Rebooting Computing week, and included invited talks from a wide range of leaders of industry, academia, and government. See here for the agenda.
Dr. Williams is Senior Fellow at HPE and Director of the Information and Quantum Systems Lab. He argues that the end of Moore’s Law scaling provides room for creative solutions that go beyond the traditional von Neumann processor. These include brain-inspired architectures, memristors, analog accelerators, and nonlinear dynamics. For example, a memristor array known as the “Dot-Product Engine” (DPE) provides much faster analog processing of Boolean algebra with much lower power than conventional digital systems. The talk by Dr. Williams is available here.
Other talks from the Industry Summit and the co-located ICRC 2017 are available here.
- Rebooting Computing Video Overview
- IEEE Future Directions
- ICRC 2018 Call for Papers
- Computing in Science and Engineering on the End of Moore's Law
- IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC)
- Arch2030 Workshop Report
- TTM 2016 Videos
- Workshop on Neuromorphic Computing
- Workshop on Beyond CMOS Technology
- Update on National Strategic Computing Initiative (NSCI)
- RC White Paper on Nanocomputers
- IEEE Computer Magazine on Rebooting Computing
- RC-ITRS Report on the Foundation of the New Computer Industry Beyond 2020