Prof. John Ousterhout of Stanford University proposes that the much faster speed of DRAM memory makes it preferable to keep the entire memory in DRAM, rather than the more conventional hard drives or flash memory, particularly for large-scale Web applications in data centers. He calls this alternative storage system “RAMCloud”. See here for a more detailed analysis.
This article by Nikonov and Young compares the performance of several different classes of emerging nanodevices, which are either electronic, ferroelectric, ferromagnetic, or magnetoelectric. This is published in the first issue of the new IEEE Journal of Exploratory Computational Devices and Circuits, an open-access online publication. See here for the other articles in this issue.
Intel and Micron Technology jointly developed a new non-volatile memory technology that uses 3D stacking to obtain 10X the density of conventional DRAM, with speed close to that of DRAM. They are expected to be available in 2016. This may offer an intermediate memory level in the hierarchy.
There are a variety of current and proposed magnetic memory technologies, but a new "magnetoelectric" device developed by researchers at UCLA uses a voltage pulse to switch the magnetic element, rather than a current pulse as for most magnetic devices. This should enable a compact, lower-power device that should be ideal for future high-density non-volatile memory arrays, which may also be integrated with logic in the same technology.
Computing Now, the IEEE Computer Society Blog, has a special introduction on radical alternatives to current computing paradigms, focusing on Quantum Computing, Biologically Inspired Computing, and NanoComputing. This introduction, in turn links to 5 earlier articles in these and related topics, from several IEEE Magazines. It also presents Additional Resources at the end with other articles and videos.
The International Technology Roadmap for Semiconductors (ITRS) is developing new approaches for future roadmaps that focus more on systems-level packaging and technology. Read More here.
ITRS has established a collaboration with IEEE Rebooting Computing to develop future plans. Read More here.
The International Solid-State Circuits Conference was held in San Francisco in February 2015. The theme was "Silicon Systems: Small Chips for Big Data". This article from the Winter 2015 issue of IEEE Solid-State Circuits Magazine describes technology trends in devices and systems being developed to meet future Big Data requirements. See also http://isscc.org/ for more information.
Sandia researcher Dr. Erik DeBenedicitis has proposed a future scalable 3D computer architecture that integrates processing with memory and storage in millions of repeated units, each on the nanometer scale. This should permit continuation of Moore's Law scaling far beyond that permitted within traditional Von Neumann architectures. This may require the use of adiabatic power approaches to reduce power density to acceptable levels. Algorithms optimized for this massively distributed parallel architecture are likely to be much faster than conventional software approaches.
A Sandia report with a more complete analysis of hardware and software issues is available here.
Stanford Professors Subhasish Mitra and Philip Wong and colleagues have developed a four-layer "High-Rise" 3D chip architecture, including the use of carbon nanotubes as electronic interconnects. This work was presented at the International Electron Devices Meeting (IEDM) in San Francisco in December.
For further details, see more here.
For a recent conference paper on this technology, read more here.
The ITRS is an international consortium sponsored by the semiconductor manufacturing industry to plan and project future trends in device and system manufacturing and integration. One of the chapters of the ITRS report is on Emerging Research Devices that will be needed to supplement CMOS devices in order go beyond the limitations of Moore's Law scaling for logic and memory in the next decade. This includes new materials, new devices, and new architectures.
The full report is available online at http://www.itrs.net/.