Delivering the Future of High-Performance Computing
At the recent DARPA Electronics Resurgence Initiative Summit, a keynote talk was given by Dr. Lisa Su of AMD, focusing on how the semiconductor industry is meeting the growing demands of future high-performance computing as Moore’s Law is slowing down.
Dr. Su explained that although Moore’s Law scaling to 5 nm is continuing, the pace of such progress is slowing down. But the performance improvement continues to develop at a rapid rate, due to a combination of three factors:
- Microarchitecture on chip
- Multi-chip packaging of chiplets
- Integration of heterogeneous processors
Optimum system performance requires co-design of silicon chips, system architecture, and software. She presented the example of the exascale computer system being developed at Oak Ridge National Lab, which should exhibit 1.5 exaflops by 2021. This is a partnership of AMD and Cray, as is further described in this HPCwire article.
While the highest-performance chips and systems will initially be limited to the most expensive machines, it is expected that similar technology will become available within a few years in data centers, edge computers, and even mobile devices.
Other videos from the Summit are available on the DARPAtv YouTube Channel.