The Tunnel FET or TFET has been identified as a possible future elementary transistor for future fast low-power applications, surpassing CMOS performance. Min and Asbeck of the University of California at San Diego have simulated such a device in a novel vertical configuration, and report the results in the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC): “Compact Modeling of Distributed Effects in 2-D Vertical Tunnel FETs and Their Impact on DC and RF Performances.” Their results indicate an 800 GHz cutoff frequency for a 20 nm channel length, even including parasitics. This is highly encouraging for high-frequency analog and digital applications.
Hewlett Packard Enterprise (HPE) has been developing a new paradigm for high-performance computing associated with Big Data, whereby an enormous multi-terabyte (TB) pool of memory is shared by many processors. This approach is known as Memory-Driven Computing, or MDC, and the project is called “The Machine”. In the latest version of the prototype, 160 TB of fast non-volatile memory is connected to forty 32-core processors via fast photonic interconnects.
An overview of the prototype is provided here.
Some potential Big-Data applications are discussed here.
For more information from HPE on Memory-Driven Computing, see here.
Tom Conte, professor of Computer Science at Georgia Institute of Technology and co-chair of the IEEE Rebooting Computing (IEEE RC) Initiative, discusses how the International Roadmap for Devices and Systems (IRDS), supported by IEEE RC, intends to guide the computing industry beyond the limitations of Moore’s Law.
Semiconductor Engineering presents an overview of recent trends in machine learning, based in part on a recent market survey. The field is undergoing a renaissance, with a variety of diverse approaches on both hardware and software levels. Systems may include heterogeneous mixtures of CPUs, GPUs, DPSs, FPGAs, and ASICs. Optimized approaches may differ between the initial learning phase and the subsequent interpretation phase (inferencing and estimation). Major current applications include autonomous vehicles and cloud-based artificial intelligence, but many other applications are starting to develop.
Computing Now, Guest Editors’ Introduction by Kevin Rudd and Richard Murphy
The authors point out that moving data between logic and memory modules is now the major source of delay and power consumption. Given new memory technologies, alternative architectures such as PIM and NDP offer opportunities for substantial enhancement in performance as well as energy efficiency for memory-intensive problems, such as those associated with Big Data.
For the article and a list of further articles and resources, see here.
A panel of semiconductor experts at the South by Southwest festival sees a future that favors power-efficient computers instead of ones with smaller transistors.
In this Engadget article, Tom Conte examines Moore’s Law, the evolution of computer circuitry, and the switch to multicore. In order to keep delivering on computing advancements, a fundamentally different approach to computing is required. The IEEE Rebooting Computing Initiative was created to study these next-gen alternatives.
The online magazine Semiconductor Engineering interviewed several leaders in Chip Fabrication, focusing on future trends in nanodevices, alternative technologies, neuromorphic architectures, and advanced packaging. The upshot is that a variety of techniques will be needed for different applications in the next decade.
Members of the RC Steering Committee contributed an article to a special issue of Mondo Digitale, a trade magazine sponsored by the Italian Association for Informatics and Automatic Computation. The article reviewed how both the RC Initiative and the new IRDS Roadmap are working to reinvent the field of computing to maintain exponential enhancement in performance beyond the end of Moore’s Law scaling. Most of the article is in English.