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Feature Article

Feature Article

IRDS™ Roadmap Executive Summary

The International Roadmap for Devices and Systems™ issued its latest roadmap report, projecting the next 15-20 years of electronic devices, circuits, and systems.

Moore’s Law scaling has been based on packing more transistors on a chip. While traditional 2D scaling is saturating, 3D scaling of vertical transistors will enable continued increase in transistor density and system performance for another 20 years. IRDS™ is projecting how this scaling will continue through the electronics and computer industry internationally, and implications for a variety of applications such as IoT, mobile, cloud, 5G, medical and automotive systems. A new focus for this year is on Cryogenic Electronics and Quantum Information Processing. For next year, a new focus will be on artificial intelligence and machine learning (AI/ML).

IRDS™ is sponsored by IEEE Rebooting Computing and IEEE Standards Association, as well as SINANO Institute in Europe, the System Device Roadmap Committee of Japan (SDRJ), and the International Electronics Manufacturing Initiative (iNEMI).

Access the IRDS™ Roadmap. The complete report has many chapters, but an overview is available via the Executive Summary. Note that while the Roadmap documents are available free of charge, users must register for the IRDS™ Technical Community.

Technology Spotlight

Technology Spotlight

Digital Annealer Chip for Optimization Problems

“Quantum-inspired” computing using custom CMOS chip at room temperature

There has been considerable attention in recent years to a superconducting quantum computer specially designed for solving combinatorial optimization problems using “quantum annealing”. But quantum annealing is a variant of simulated annealing, which is a well-known method for solving similar optimization problems using a classical digital computer. However, a standard microprocessor is not configured to solve such a problem efficiently, particularly when the data set becomes very large. A custom architecture with distributed memory and parallelism might be much faster.

With that in mind, Fujitsu developed a “digital annealing unit” (DAU), a custom CMOS chip with an architecture designed to address large-scale optimization problems more efficiently. This has been called “quantum-inspired”, but it is really a standard CMOS chip similar to an FPGA. The first-generation digital annealer chip was introduced last year, and was described in IEEE Spectrum. The second-generation chip, for somewhat larger data sets, was introduced recently.

View a video introduction to the Fujitsu Digital Annealer and a video overview of applications for the digital annealer. Further information is available from Fujitsu.

In comparison, D-Wave Systems is selling an alternative Quantum Annealer based around a superconducting chip cooled to -273 C. The latest generation of this quantum annealer is described in Communications of the ACM. While a quantum annealer may in principle solve problems much faster than a classical annealer, this advantage has not yet been convincingly demonstrated in real systems.

Whether these systems are quantum or “quantum-inspired”, they provide novel processors for future Big Data problems.