- Digital Annealer Chip for Practical Optimization Problems - Fujitsu markets CMOS accelerator chip that uses “quantum-inspired” algorithms.
- Quantum No Threat to Supercomputing As We Know It - Cray and others see no major impact for at least 10 years
- How the Spectre and Meltdown Hacks Really Worked - Speculative Execution enables CPUs to work faster, but opens the door to attacks.
- New US Government Initiative in Artificial Intelligence - White House announcement proposes to coordinate efforts in government, industry, and academia, to support R&D and education in the field of AI.
- IBM Announces IBM Q System One quantum computing platform - Superconducting 20-qubit platform will be available to outside users via the cloud.
- IEEE Computer Society Predicts Top 10 Trends for 2019 - Accelerators for Deep Learning lead the list.
- US National Quantum Initiative Approved - Provides $1.2B over 5 years to promote quantum information science at government agencies, and coordinate with R&D in academia and industry.
- IBM Reveals 8-Bit Analog Chip with Phase-Change Memory - Designed for integration with neural nets.
- In-Memory Computing Chip as AI Accelerator - Princeton University researchers designed and demonstrated analog neural network integrated with CPU.
- Europe Launches Quantum Flagship R&D Project - 10-year, 1B€ program includes quantum computing, communication, simulation, and sensing.
New Report on the Future of Heterogeneous Computing from US Dept. of Energy
Follows 2018 Workshop on Extreme Heterogeneity led by Oak Ridge National Lab
In the past decade, the nature of high performance computing has changed. Previously, HPC relied on CPUs, the performance of which was growing exponentially according to Moore’s Law. With that ending, continued growth in performance must rely on extremely heterogeneous computer architectures that incorporate increasing numbers of CPUs, GPUs, accelerators, FPGAs, connected with a variety of memory systems and interconnects. This has led to a series of challenges to HPC users, which must be addressed in order to use these new resources most effectively. This workshop, chaired by Dr. Jeffrey Vetter of Oak Ridge National Lab, identified areas of R&D to overcome these problems, and suggested that machine learning should be applied to optimizing the diversity of processors available to specific computations.
An overview of the report is presented here
Information on the DoE Workshop is available here
A complete copy of the report is available here
Hardware-Software Co-Design for Analog-Digital Accelerator for Machine Learning
At the recent IEEE International Conference on Rebooting Computing, held in Washington DC in November as part of IEEE Rebooting Computing Week, one of the presentations was by Dr. Dejan Milojicic of Hewlett Packard Labs. Dr. Milojicic is also a co-chair of the IEEE Rebooting Computing Initiative.
Dr. Milojicic spoke about an R&D project to demonstrate a prototype accelerator for machine learning, including both the hybrid analog-digital hardware and the entire software stack. This is a collaboration between Hewlett Packard Enterprise and academic researchers at the University of Illinois and Purdue.
The core of the accelerator is a crossbar array of memristors, which are used for analog computation of matrix operations, with application to neural networks for machine learning. However, the system also includes key CMOS digital circuits closely integrated with the memristors. The talk emphasized how software co-design with the hardware is essential for developing applications. The software stack consists of an Open Neural Network Exchange converter (ONNX), an application optimizer, a compiler, a driver, and emulators. While this system is not yet a commercial product, it is approaching the stage where it will become available for developing inference applications for machine learning.
Videos of other ICRC 2018 talks are available from IEEE.tv here.
The Proceedings of ICRC 2018 is available from IEEE Xplore here.
- Rebooting Computing Video Overview
- IEEE Future Directions
- Computing in Science and Engineering on the End of Moore's Law
- IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC)
- Arch2030 Workshop Report
- Workshop on Neuromorphic Computing
- Workshop on Beyond CMOS Technology
- Update on National Strategic Computing Initiative (NSCI)
- RC White Paper on Nanocomputers
- IEEE Computer Magazine on Rebooting Computing
- RC-ITRS Report on the Foundation of the New Computer Industry Beyond 2020