- NSF Seeks Public Input on Updated National Strategic Computing Initiative - Deadline for online submission of comments is 23 August.
- Wafer-Scale Fabrication of 3D Carbon Nanotube Chips - Integrated with RRAM memory arrays
- Processing in Memory to Reduce Power - Non-von-Neumann architecture could be key to low-power machine learning.
- Photonic Neural Network - Researchers in Germany and UK demonstrate pattern recognition in all-optical chip.
- Microsoft Open Source Quantum Computing Software - Q# language and quantum development kit enable programming quantum simulators.
- Intel’s View of the Chiplet Revolution - Packaging of multiple chiplets with high-speed interconnects to enhance performance, density, and reliability.
- Ion-Based Quantum Computing - New company IonQ uses integrated traps of single ions, linked by laser beams, without requiring cryogenic cooling.
- Digital Annealer Chip for Practical Optimization Problems - Fujitsu markets CMOS accelerator chip that uses “quantum-inspired” algorithms.
- Quantum No Threat to Supercomputing As We Know It - Cray and others see no major impact for at least 10 years
- How the Spectre and Meltdown Hacks Really Worked - Speculative Execution enables CPUs to work faster, but opens the door to attacks.
- IEEE Computer Society Predicts Top 10 Trends for 2019 - Accelerators for Deep Learning lead the list.
Superconducting Neurons Could Match the Power Efficiency of the Brain
MIT Technology Review features a new research paper from MIT and Colgate University on ultra-low-power electronic neurons based on superconducting nanowires. Read an overview of the research at MIT Technology Review.
Based on the switching properties of 100-nm-wide superconducting nanowires, the researchers have developed a superconducting neuron with a firing threshold, a refractory period, and a travel time that can be adjusted according to the circuit design. Furthermore, this superconducting neuron can also be used to trigger or inhibit other neurons via a synapse, with a significant fanout capability.
Simulations show that a neuromorphic computing system based on these superconducting neurons and synapses should have a figure of merit (synaptic operations per second per watt) of more than 1014. This includes an estimate of the cooling power required for cryogenic devices. This is comparable to the figure of merit for biological brains, but four orders of magnitude larger than the corresponding values for semiconducting neuromorphic computers, due to the very low power of superconducting devices and interconnects. Furthermore, the superconducting neurons are much faster than biological neurons, and are also faster than semiconducting neurons. While this initial research was mostly theoretical, it is promising for the development of a superconducting neuromorphic computer.
A preprint of the research article, “A Power-Efficient Artificial Neuron Using Superconducting Nanowires”, by Emily Toomey, Ken Segall, and Karl Berggren, is available at arXiv.org.
Overview of IRDS™ Chapter on Beyond CMOS and Emerging Research Materials
The International Nanodevices and Computing Conference (INC 2019) was recently held in Grenoble France, 2-5 April 2019. This was co-sponsored by IRDS™, IEEE Rebooting Computing, and the European SiNANO Institute. See the conference program on the INC 2019 website.
INC 2019 included outbriefs of the key results from the new IRDS™ Roadmap, which is now available online. An overview of the latest IRDS™ report is available on HPCwire. An overview of the Beyond CMOS chapter is available on the IRDS™ website.
The talks from INC 2019 were recorded and are available on IEEE.tv.
Dr. Shamik Das of Mitre Corporation presented an overview of the Beyond CMOS chapter of the IRDS™ Roadmap. The objective of Beyond CMOS is to promote future devices that can support the application drivers of future computation requirements, including exascale, Big Data, IoT, and AI. Dr. Das focuses on technology updates in emerging memory devices, logic and information processing devices, then closes with a summary of device-architecture-system interactions. Novel analog and optical components as well as novel materials will need to be integrated closely with silicon.
The video presentation by Dr. Das is available on IEEE.tv.
- Rebooting Computing Video Overview
- IEEE Future Directions
- Computing in Science and Engineering on the End of Moore's Law
- IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC)
- Arch2030 Workshop Report
- Workshop on Neuromorphic Computing
- Workshop on Beyond CMOS Technology
- Update on National Strategic Computing Initiative (NSCI)
- RC White Paper on Nanocomputers
- IEEE Computer Magazine on Rebooting Computing
- RC-ITRS Report on the Foundation of the New Computer Industry Beyond 2020