- Intel develops new cryptography protocols - Designed to be resistant to hacking by future quantum computers
- New memristor device acts like biological neuron - May provide basic element for neuromorphic computing
- Record speeds for AI inferencing - Nvidia GPU exceeds prior benchmark performance
- Analog Optical Computing Chip for Neural Networks - Carries out multiply-accumulate computations in silicon photonic chip for AI.
- US Government Announces New Research Centers in AI and QC - $1B in government labs and universities funded by National Science Foundation and Dept. of Energy.
- Newsletter of IEEE Electron Devices Society features new IRDS™ Roadmap - Provides history of earlier semiconductor roadmaps and an overview of the latest roadmap.
- US Government funds 3 academic-based institutes on quantum information - $75M over five years going to research based at the University of Colorado, University of California at Berkeley, and the University of Illinois.
- Chip Proposals Seek to Revive US Manufacturing - US Congress proposes aid to advance US semiconductor industry.
- CCC Report on Embedded Security Research - Conclusions of Computing Community Consortium Workshop on Embedded Security in Connected Devices.
- DARPA Kicks Off Program in Quantum Computing - University-industry teams will investigate hybrid classical-quantum optimization algorithms.
- RAND Study Advocates Post-Quantum Cryptography - New report proposes development of communication security protocols that are more resistant against future quantum computers.
- Silicon Spin Qubits Demonstrated - Researchers fabricate silicon quantum dots that can operate at temperatures above 1 K.
The Edge-to-Cloud Continuum
Virtual Roundtable with Experts from Industry and Academia
In the November issue of IEEE Computer, Dejan Milojicic of Hewlett Packard Labs interviewed several experts on computer system architectures (visit IEEE Xplore for the interview), on the subject of the future of edge computing, cloud computing, and how they will work together.
The panelists included Tom Bradicich of HP, Adam Drobot of OpenTechWorks, and Ada Gavrilovska of Georgia Tech.
Cloud computing refers to computing in large-scale data centers, while edge computing takes place at least partly in cell phones, laptops, desktops, and the Internet-of-Things.
While Cloud computing is often more computationally efficient, issues of latency and bandwidth generally require some data processing at the edge. In many cases, these are mobile devices, so that wireless protocols of 5G and beyond are essential. There are also important issues of security, privacy, and reliability at both levels and in the communication between the two. In most cases, there will be a variety of tradeoffs, depending on the type of application and on business considerations.
These issues are likely to continue to generate a dynamic computing environment for the foreseeable future.
Types of Deep Learning Hardware
Interview with Bradley Geden of Synopsys
Artificial intelligence based on “deep learning” is rapidly being implemented in a wide variety of edge systems, mostly using commercial chips that are one of several types. Ed Sperling, Editor of Semiconductor Engineering, interviewed Bradley Geden of Synopsys about these different types, and the various applications for each type.
These include systolic arrays, 2D course-grained reconfigurable arrays, and parallel pipelines. In each case, there is a 2D neural network array of artificial neurons, with matrix operations (multiply-accumulates or MACs) on the values in the neurons. These are all digital computational arrays, in contrast to analog arrays of memristors that are under development elsewhere.
Systolic arrays are hard-wired for MAC operations, and are used for basic image recognition neural networks. The reconfigurable arrays are more like FPGAs, with greater flexibility for a wider range of algorithms, but are more complex to program. Parallel pipelines are optimized for high-speed throughput, involving complex calculations on real-time data.
Mr. Geden also emphasized design synthesis approaches for programming these chips. Given the repetitive nature of these structures, a hierarchical approach may often be more flexible and easier to alter than a “flat” approach. Further information from Synopsys on design tools for AI systems is available at the Synopsys website.
For further details, watch the video.
- Rebooting Computing Video Overview
- IEEE Future Directions
- IEEE Future Directions Blog
- Computing in Science and Engineering on the End of Moore's Law
- IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC)
- Arch2030 Workshop Report (PDF, 948 KB)
- Workshop on Neuromorphic Computing
- Workshop on Beyond CMOS Technology
- Update on National Strategic Computing Initiative (NSCI)
- RC White Paper on Nanocomputers
- IEEE Computer Magazine on Rebooting Computing
- RC-ITRS Report on the Foundation of the New Computer Industry Beyond 2020 (PDF, 947 KB)